1. Field of the Invention
The present invention relates generally to a semiconductor device and a fabricating method thereof.
2. Description of the Related Art
Recently, with the increasing demand for having a larger-capacity, higher-performance semiconductor device, multiple input/output terminals are required for constituting a semiconductor device. Furthermore, due to the trend towards smaller semiconductor devices in size, as well as the formation of multiple input/output terminals, there is a limit on the spacing density of the input/output terminals.
To address this problem, a wafer level package (WLP) structure in which conductive bumps are directly formed on top surfaces of semiconductor dies has been developed. However, the developed WLP structure suffers from the complexity in controlling the number and pitch spacing of conductive bumps due to presence of the conductive bumps, which are made of a solder material, making the WLP structure bulky. Therefore, the conventional WLP structure is not suitable for achieving fine pitch conductive bumps.